The present invention relates to a memory device, and more specifically to a high-speed memory device.
Conventionally, a synchronous memory device, an external clock frequency and an internal operation frequency of which are equal to each other, is used for both write and read operations. FIGS. 1 and 2 are a block diagram showing the structure of a conventional memory device, and a timing diagram illustrating timing waveforms of a read operation.
The memory device shown in FIG. 1 consists of a memory cell array 1, a row decoder 2, a column decoder 3, an address input 4 and an external input/output section 12.
The external input/output section 12 is the section through which data from outside is written in the memory device, and data is read from the memory device. Such a section is generally called the input/output section (to be called I/O hereinafter) of a memory device; however, in this description, the section will be called external I/O so as to clarify the contrast between the structure of the conventional technique and that of the present invention.
The external bit width 12a shown in the diagram indicates the number of data (number of I/O) which can access the memory device at the same time, and the internal bit width 11 indicates the number of data which can be accessed by an address set.
As can be seen in FIG. 1, in the conventional semiconductor memory device, an internal bit width 11 and an external bit width 12a are not particularly distinguished from each other, but both internal bit width 11 and external bit width 12a are set to, for example, 4 bit. That is, simply, four lines are connected to the I/O of the memory device.
FIG. 2 is a timing diagram illustrating the read operation of the conventional memory device. As shown in this figure, address data A.sub.0, A.sub.1, A.sub.2, . . . , are input in synchronism with an external clock. The internal clock frequency used for controlling the internal operation of the memory device is equal to the external clock frequency, and therefore write data Q.sub.0, Q.sub.1, written in a memory cell array are read from an external I/O in synchronism with the external clock frequency.
FIG. 3 is a timing diagram illustrating the write operation of the conventional memory device. As shown in this figure, address data A.sub.0, A.sub.1, A.sub.2, . . . , are address input data in synchronism with an external clock. In similar to the read case, the internal clock frequency used for controlling the internal operation is equal to the external clock frequency, and therefore write data D.sub.0, D.sub.1, D.sub.2, . . . , are written in a memory cell array in synchronism with the external clock frequency.
As described above, in the read and write operations of the conventional device, the internal operation frequency is set equal to the external clock frequency. With such a structure, for example, even when the memory device is operable for a frequency region higher than the external clock frequency, the operation is limited by the external clock frequency and cannot fully exhibit its high-speed performance.
More specifically, for example, when the memory device is assembled on a board, I/O data including an external clock, an address signal, and read/write data, are transmitted on the board, and therefore the repetition frequencies of these signals are inevitably limited by the upper frequency limit of the board.
Recently, as the miniaturization of the semiconductor memory device proceeds, the internal operation frequency of the device is improved so remarkably that the device, in many times, exhibits a high speed performance which exceeds the upper frequency limit of the board. In such a case, it is extremely important to have a technique for realizing the high speed operation of the whole system including the memory device itself assembled on the board, by rendering the memory device internally operate beyond the frequency limit of the board.
Apart from the above, the conventional semiconductor memory device is known to entail the following drawback, in the function test on the device. That is, after the completion of a wafer process, the function of the memory device formed on the silicon wafer is tested with a die sorting tester. However, mainly due to the upper limitation of the frequency of the prober, the speed selection and function selection of the memory device on the silicon wafer cannot be executed at the same time.
It should be noted here that the die sorting test is a function test for an integrated circuit on a silicon wafer, conducted in a comparatively lower frequency range, and more specifically, a die having a function fault is marked with use of a prober, and a chip containing the function fault is selected after die separation.
Generally, the high frequency characteristics of a prober used in a die sorting test are significantly low as compared to the high frequency performance of the test stage equipped in a large sized high speed tester. Under these circumstances, the below-described measures are taken in the conventional die sorting test. More specifically, first, only the selection of a die containing a function fault is carried out in comparatively lower frequency range. Then, the speed selection is carried out in the following manner. That is, a silicon wafer is cut off into chips, and those chips which passed the function selection by the die sorting test are sealed in excellent high speed packages. After that, the packages are once again mounted to the test stage of the high speed tester, to be subjected to the function selection including the operation speed.
As described above, conventionally, in the die sorting test before sealing in a package, the assurance of the function is possible only at lower speed, that is, impossible at high speed. In other words, conventionally, the full range of the operation frequency cannot be assured. As a result, in the case where chips are sealed in the packages after a die sorting test, and an operation frequency test is carried out with use of the large sized high speed tester, the operation frequency range, in some cases, does not reach the specification value. Thus, the conventional technique entails the drawback of a cost of using the large sized high speed tester and a cost of the expensive high speed packages discarded together with defective devices, which cause a high cost for the nondefective device.